Field of the Invention
The present invention relates to the calibration of communication channel parameters in systems, including mesochronous systems, in which two (or more) components communicate via an interconnection link; and to the calibration needed to account for drift of conditions related to such parameters during operation of the communication channels.
Description of Related Art
In mesochronous communication channels, typically a reference clock provides frequency and phase information to the two components at either end of the link. A transmitter on one component and a receiver on another component each connect to the link. The transmitter and receiver operate in different clock domains, which have an arbitrary (hut fixed) phase relationship to the reference clock. The phase relationship between transmitter and receiver is chosen so that the propagation delay seen by a signal wavefront passing from the transmitter to the receiver will not contribute to the timing budget for signaling rate. Instead, the signaling rate is determined primarily by the drive window of the transmitter and the sample window of the receiver. The signaling rate will also be affected by a variety of second order effects. This system is clocked in a mesochronous fashion, with the components locked to specific phases relative to the reference clock, and with the drive timing point and sample timing point of each link fixed to the phase values that maximize the signaling rate.
These fixed phase values may be determined in a number of ways. A sideband link may accompany a data link (or links), permitting phase information to be passed between transmitter and receiver. Alternatively, an initialization process may be invoked when the system is first given power, and the proper phase values determined by setting a transmitter drive timing point, and executing a calibration sequence that includes passing a calibration pattern or calibration patterns across the actual link to the receiver, and adjusting the receiver sample timing point until the data is successfully sampled at the receiver. Once the drive timing point and sample timing point of each link have been fixed, the system is permitted to start normal operations. The calibration sequences used to establish proper phase values on initialization are designed to provide reliable results over a wide variety of environmental conditions, and a wide variety of operating conditions on the communication link. To provide reliable results, the calibration sequences pass a calibration pattern or calibration patterns that include lots of data and take quite a long time.
The calibration sequences use patterns with long or numerous codes designed to find the worst-case leading edge and the worst-case trailing edge of a passing region for a parameter subject of the calibration, such as drive timing points and sample timing points discussed above. The edge values are a function of many system parameters including for example silicon processing variations, and packaging parameters such as crosstalk, terminal resistance accuracy, system board impedance, module impedance, trace lengths, connector locations, and so on. In addition to the uncertainty of these variables, the patterns necessary to create worst-case inter-symbol interference or resonance can be very long, and are difficult to predict. In order to deal with the uncertainty of which patterns will generate the leading or trailing edge of the worst-case passing region, many systems use a brute force approach to calibration sequences, using sequences with very long calibration patterns. For example, one brute force approach is based on the use of a pseudorandom bit sequence PRBS, which consists of a long, fairly random pattern, to attempt to determine the passing region. Other systems utilize many initialization patterns that are hundreds of bits long to present the worst-case pattern for a given configuration, and attempt to cover all possible conditions.
The use of long, complex patterns is generally adequate if the calibration sequence is run infrequently. For example, if the algorithm is run only during an initial system bring up, the length of the calibration pattern is not generally critical. However, during normal operation, system conditions will change. Ambient temperature, component temperature, supply voltages, and reference voltages will drift from their initial values. Also, spread spectrum clock systems intentionally shift the clock frequency to meet emission standards. As the conditions drift, the optimal timing points of the transmitter and receiver and other parameters will change.
Although the calibration sequences can be run periodically to adjust for drift, the length and complexity of the patterns and the algorithms used in the sequences interfere with mission-critical operations of the system. Primarily, the long calibration sequences with patterns having long or numerous codes require storage, access to the input/output circuits and interconnect, and processing resources in order to complete a calibration sequence. During this recalibration time, the system is unavailable to the application. This creates at least two significant problems. First, performance is reduced, in general. Second, many applications can tolerate only minimum latency addition without under or over running their streaming data.
It is desirable to provide techniques to compensate for the condition drift, and provide improvements in system and component design to permit these techniques to be utilized.